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cat130xx ? 2007 catalyst semiconductor, inc. 1 doc. no. 1121 rev. a characteristics subject to change without notice voltage supervisor with microwire serial cmos eeprom features ? precision power supply voltage monitor ? 5v, 3.3v, 3v & 2.5v systems ? 7 threshold voltage options ? active high or low reset ? valid reset guaranteed at v cc = 1 v ? high speed operation ? selectable x8 or x16 memory organization ? low power cmos technology ? 1,000,000 program/erase cycles ? 100 year data retention ? industrial temperature range ? rohs-compliant 8-pin soic package for ordering information details, see page 13. pin configuration soic (w) cs 1 8 v cc sk 2 7 rst/ rst di 3 6 org do 4 5 gnd pin function pin name function cs chip select sk clock input di serial data input do serial data output gnd ground org memory organization rst/ rst reset output v cc power supply description the cat130xx (see table below) are memory and supervisory solutions for microcontroller based systems. a cmos serial eeprom memory and a system power supervisor with brown-out protection are integrated together. memory interface is via microwire serial protocol. the cat130xx provides a precision v cc sense circuit with two reset output options: cmos active low output or cmos active high. the reset output is active whenever v cc is below the reset threshold or falls below the reset threshold voltage. the power supply monitor and reset circuit protect system controllers during power up/down and against brownout conditions. seven reset threshold voltages support 5v, 3.3v, 3v and 2.5v systems. if power supply voltages are out of tolerance reset signals become active, preventing t he system microcontroller, asic or peripherals from operating. reset signals become inactive typically 240ms after the supply voltage exceeds the reset threshold level. memory size selector product memory density 13001 1-kbit 13004 4-kbit 13008 8-kbit 13016 16-kbit threshold suffix selector nominal threshold voltage threshold suffix designation 4.63v l 4.38v m 4.00v j 3.08v t 2.93v s 2.63v r 2.32v z note: when the org pin is connected to v cc , the x16 organization is selected. when it is connected to ground, the x8 pin is selected. if the org pin is left unconnected, t hen an internal pullup device will select the x16 organization.
cat130xx ? 2007 catalyst semiconductor, inc. 2 doc. no. 1121 rev. a characteristics subject to change without notice block diagram absolute maximum ratings (1) parameters ratings units storage temperature -65 to +150 c voltage on any pin with respect to ground (2) -0.5 to +6.5 v reliability characteristics (3) symbol parameter min units nend (4) endurance 1,000,000 program/ erase cycles tdr data retention 100 years d.c. operating characteristics v cc = +2.5v to +5.5v unless otherwise specified. limits symbol parameter min. typ. max. test condition units i cc supply current 3 read or write at 1mhz ma 12 25 v cc < 5.5v; all i/o pins at v ss or v cc i sb standby current 10 20 v cc < 3.6v; all i/o pins at v ss or v cc a i l i/o pin leakage 2 pin at gnd or v cc a v il input low voltage -0.5 0.8 v v ih input high voltage 2.0 v cc + 0.5 v v ol output low voltage 0.4 v cc 2.5v, i ol = 2.1ma v v oh output high voltage 2.4 v cc 4.5v, i oh = -0.4ma v notes: (1) stresses above those listed under ?absol ute maximum ratings? may cause permanent damage to the device. these are stress ra tings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sectio ns of this specification is not implied. exposure to any absolute maximum rating for extended pe riods may affect device performance and re liability. (2) the dc input voltage on any pin should not be lower than -0.5 v or higher than v cc + 0.5 v. during transitions, the voltage on any pin may undershoot to no less than -1.5 v or overshoot to no more than v cc + 1.5 v, for periods of less than 20 ns. (3) these parameters are tested initially and after a design or process change that affects the parameter according to appropr iate aec-q100 and jedec test methods. (4) block mode, v cc = 5 v, 25c do eeprom org cs sk di v cc voltage detector rst or rs t v ss
cat130xx ? 2007 catalyst semiconductor, inc. 3 doc. no. 1121 rev. a characteristics subject to change without notice a.c. characteristics (memory) (1) v cc = +2.5v to 5.5v, t a = -40c to 85c, unless otherwise specified. symbol parameter min max units f sk clock frequency dc 2000 khz t css cs setup time 50 ns t csh cs hold time 0 ns t csmin minimum cs low time 0.25 s t skhi minimum sk high time 0.25 s t sklow minimum sk low time 0.25 s t dis di setup time 100 ns t dih di hold time 100 ns t pd1 output delay to 1 0.25 s t pd0 output delay to 0 0.25 s t hz (1) output delay to high-z 100 ns t sv output delay to status valid 0.25 s t ew program/erase pulse width 5 ms t pu (2), (3) power-up to ready mode 1 ms notes : (1) test conditions according to ?a.c. test conditions? table. (2) tested initially and after a design or pr ocess change that affects this parameter. (3) t pu is the delay between the time v cc is stable and the device is ready to accept commands. a.c. test conditions input rise and fall times 50 ns input levels 0.4v to 2.4v (4.5v < v cc < 5.5v) input levels 0.2v cc to 0.7v cc (2.5v < v cc < 4.5v) timing reference levels 0.8v, 2.0v (4.5v < v cc < 5.5v) timing reference levels 0.5v cc (2.5v < v cc < 4.5v) output load current source: i ol max / i oh max ; c l = 100pf
cat130xx doc. no. 1121 rev. a 4 ? 2007 catalyst semiconductor, inc. characteristics subject to change without notice electrical characteristic s (supervisory function) v cc = full range, t a = -40oc to +85oc unless otherw ise noted. typical values at t a = +25oc and v cc = 5v for l/m/j versions, v cc = 3.3v for t/s versions, v cc = 3v for r version and v cc = 2.5v for z version. symbol parameter threshold conditions min typ max units t a = +25oc 4.56 4.63 4.70 l t a = -40oc to +85oc 4.50 4.75 t a = +25oc 4.31 4.38 4.45 m t a = -40oc to +85oc 4.25 4.50 t a = +25oc 3.93 4.00 4.06 j t a = -40oc to +85oc 3.89 4.10 t a = +25oc 3.04 3.08 3.11 t t a = -40oc to +85oc 3.00 3.15 t a = +25oc 2.89 2.93 2.96 s t a = -40oc to +85oc 2.85 3.00 t a = +25oc 2.59 2.63 2.66 r t a = -40oc to +85oc 2.55 2.70 t a = +25oc 2.28 2.32 2.35 v th reset threshold voltage z t a = -40oc to +85oc 2.25 2.38 v symbol parameter conditions min typ (1) max units reset threshold tempco 30 ppm/oc t rpd v cc to reset delay (2) v cc = v th to (v th -100mv) 20 s t purst reset active timeout period t a = -40oc to +85oc 140 240 460 ms v cc = v th min, i sink = 1.2 ma r/s/t/z 0.3 v cc = v th min, i sink = 3.2 ma j/l/m 0.4 v ol reset output voltage low (push-pull, active low, cat130xx9) v cc > 1.0v, i sink = 50a 0.3 v v cc = v th max, i source = -500a r/s/t/z 0.8v cc v oh reset output voltage high (push-pull, active low, cat130xx9) v cc = v th max, i source = -800a j/l/m v cc - 1.5 v v cc > v th max, i sink = 1.2ma r/s/t/z 0.3 v ol reset output voltage low (push-pull, active high, cat130xx1) v cc > v th max, i sink = 3.2ma j/l/m 0.4 v v oh reset output voltage high (push-pull, active high, cat130xx1) 1.8v < v cc v th min, i source = -150a 0.8v cc v notes : (1) production testing done at t a = +25oc; limits over temperature guaranteed by design only. (2) reset output for the cat130xx9; reset output for the cat130xx1.
cat130xx ? 2007 catalyst semiconductor, inc. 5 doc. no. 1121 rev. a characteristics subject to change without notice pin description reset/reset : the reset output is available in two versions: cmos active low (cat130xx9) and cmos active high (cat130xx1). both versions are push-pull outputs for high efficiency. di: the serial data input pin accepts op-codes, addresses and data. the input data is latched on the rising edge of the sk clock input. do: the serial data output pin is used to transfer data out of the device. the data is shifted out on the rising edge of the sk clock. sk: the serial clock input pin accepts the clock provided by the host and used for synchronizing communication between host and cat130xx device. cs: the chip select input pin is used to enable/disable the cat130xx. when cs is high, the device is selected and accepts op-codes, addresses and data. upon receiving a write or erase instruction, the falling edge of cs will start the internal write cycle to the selected memory location. org: the memory organization input selects the memory configuration as either register of 16 bits (org tied to v cc or floating) or 8 bits (org connected to gnd). device operation the cat130xx products combine the accurate voltage monitoring capabilities of a standalone voltage supervisor with the high quality and reliability of standard eeproms from catalyst semiconductor. reset controller description the reset signal is asserted low for the cat130xx9 and high for the cat130xx1 when the power supply voltage falls below the threshold trip voltage and remains asserted for at least 140ms (t purst ) after the power supply voltage has risen above the threshold. reset output timing is shown in figure 1. the cat130xx devices protect ps against brownout failure. short duration v cc transients of 4 sec or less and 100mv amplitude typically do not generate a reset pulse. figure 2 shows the maximum pulse duration of negative-going v cc transients that do not cause a reset condition. as the amplitude of the transient goes further below the threshold (increasing v th - v cc ), the maximum pulse duration decreases. in this test, the v cc starts from an initial voltage of 0.5v above the threshold and drops below it by the amplitude of the overdrive voltage (v th - v cc ). figure 2. maximum transient duration without causing a reset pulse vs. overdrive voltage fi g ure 1. reset output timin g v cc purst t purst t rpd t rvalid v v th rese t rese t cat130xx9 cat130xx1 rpd t transient du r ation [s] reset overdrive v th - v cc [mv] t amb = 25oc cat130xxm cat130xxz
cat130xx doc. no. 1121 rev. a 6 ? 2007 catalyst semiconductor, inc. characteristics subject to change without notice embedded eeprom operation the cat130xx has a nonvolatile embedded memory intended for use with industry standard micropro? cessors. the memory can be organized as either registers of 16 bits or 8 bits. the cat130xx operates on a single power supply and will generate on chip the high voltage required during any write operation. the format for all instructions sent to the device is a logical ?1? start bit, a 2-bit (or 4-bit) opcode, 6-bit (13001) / 8-bit (13004) / 9-bit (13008) / 10-bit (13016) address (an additional bit when organized as x8) and for write operations a 16-bit data field (8-bit for x8 organization). the instruction format is shown in instruction set table. instruction set address data instruction device start bit opcode x 8 x 16 x 8 x 16 comments 13001 1 10 a6-a0 a5-a0 13004 1 10 a8-a0 a7-a0 13008 1 10 a9-a0 a8-a0 read 13016 1 10 a10-a0 a9-a0 read address an-a0 13001 1 11 a6-a0 a5-a0 13004 1 11 a8-a0 a7-a0 13008 1 11 a9-a0 a8-a0 erase 13016 1 11 a10-a0 a9-a0 clear address an-a0 13001 1 01 a6-a0 a5-a0 d7-d0 d15-d0 13004 1 01 a8-a0 a7-a0 d7-d0 d15-d0 13008 1 01 a9-a0 a8-a0 d7-d0 d15-d0 write 13016 1 01 a10-a0 a9-a0 d7-d0 d15-d0 write address an-a0 13001 1 00 11xxxxx 11xxxx 13004 1 00 11xxxxxxx 11xxxxxx 13008 1 00 11xxxxxxxx 11xxxxxxx ewen 13016 1 00 11xxxxxxxxx 11xxxxxxxx write enable 13001 1 00 00xxxxx 00xxxx 13004 1 00 00xxxxxxx 00xxxxxx 13008 1 00 00xxxxxxxx 00xxxxxxx ewds 13016 1 00 00xxxxxxxxx 00xxxxxxxx write disable 13001 1 00 10xxxxx 10xxxx 13004 1 00 10xxxxxxx 10xxxxxx 13008 1 00 10xxxxxxxx 10xxxxxxx eral 13016 1 00 10xxxxxxxxx 10xxxxxxxx clear all addresses 13001 1 00 01xxxxx 01xxxx d7-d0 d15-d0 13004 1 00 01xxxxxxx 01xxxxxx d7-d0 d15-d0 13008 1 00 01xxxxxxxx 01xxxxxx x d7-d0 d15-d0 wral 13016 1 00 01xxxxxxxxx 01xxxxxx xx d7-d0 d15-d0 write all addresses
cat130xx ? 2007 catalyst semiconductor, inc. 7 doc. no. 1121 rev. a characteristics subject to change without notice instructions, addresses, and write data are clocked into the di pin on the risi ng edge of the clock (sk). the do pin is normally in a high impedance state except when reading data from the device, or when checking the ready/busy status during a write operation. the serial communication protocol follows the timing shown in figure 3. the ready/busy status can be determined after the start of internal write cycl e by selecting the device (cs high) and polling the do pin; do low indicates that the write operation is not completed, while do high indicates that the device is ready for the next instruction. if necessary, the do pin may be placed back into a high impedance state during chip select by shifting a dummy ?1? into the di pin. the do pin will enter the high impedance state on the rising edge of the clock (sk). placing the do pin into the high impedance state is recommended in applications where the di pin and the do pin are to be tied together to form a common di/o pin. the ready/busy flag can be disabled only in ready state; no change is allowed in busy state. read upon receiving a read command and an address (clocked into the di pin), the do pin of the cat130xx will come out of the high impedance state and, after sending an initial dummy zero bit, will begin shifting out the data addressed (msb first). the output data bits will toggle on the rising edge of the sk clock and are stable after the specified time delay (t pd0 or t pd1 ). the read instruction timing is illustrated in figure 4. for the cat13004/08/16, after the initial data word has been shifted out and cs remains asserted with the sk clock continuing to toggle, the device will auto- matically increment to the next address and shift out the next data word in a sequential read mode. as long as cs is continuously asserted and sk continues to toggle, the device will keep incrementing to the next address automatically until it reaches to the end of the address space, then loops back to address 0. in the sequential read mode, only the initial data word is preceeded by a dummy zero bit. all subsequent data words will follow without a dummy zero bit. figure 3. sychronous data timing figure 4. read instruction timing sk di cs d o t dis t pd0, t pd1 t csmin t css t dis t dih t skhi t csh valid valid data valid t sklow sk cs di do t csmin standby t hz high-z high-z 11 0 a n a n-1 a 0 0 d n d n-1 d 1 d 0 t pd0
cat130xx doc. no. 1121 rev. a 8 ? 2007 catalyst semiconductor, inc. characteristics subject to change without notice erase/write enable and disable the cat130xx powers up in the write disable state. any writing after power-up or after an ewds (write disable) instruction must first be preceded by the ewen (write enable) instruction. once the write instruction is enabled, it will remain enabled until power to the device is removed, or the ewds instruction is sent. the ewds instruction can be used to disable all cat130xx write and erase instructions, and will prevent any accidental writing or cl earing of the device. data can be read normally from the device regardless of the write enable/disable status. the ewen and ewds instructions timing is shown in figure 5. write after receiving a write command (figure 6), address and the data, the cs (chip select) pin must be deselected for a minimum of t csmin . the falling edge of cs will start the self clocking for auto-clear and data store cycles on the memory location specified in the instruction. the clocking of the sk pin is not necessary after the device has entered the self clocking mode. the ready/busy status of the cat130xx can be determined by selecting the device and polling the do pin. since this device features auto-clear before write, it is not necessary to erase a memory location before it is written into. figure 5. ewen/ewds instruction timing figure 6. write instruction timing cs di standby 10 0 * * enable=11 disable=00 sk sk cs di do t csmin standby high-z high-z 101 a n a n-1 a 0 d n d 0 busy ready status verify t sv t hz t ew
cat130xx ? 2007 catalyst semiconductor, inc. 9 doc. no. 1121 rev. a characteristics subject to change without notice erase upon receiving an erase command and address, the cs (chip select) pin must be deasserted for a minimum of t csmin (figure 7). the falling edge of cs will start the self clocking clear cycle of the selected memory location. the clocking of the sk pin is not necessary after the device has entered the self clocking mode. the ready/busy status of the cat130xx can be determined by selecting the device and polling the do pin. once cleared, the content of a cleared location returns to a logical ?1? state. erase all upon receiving an eral command (figure 8), the cs (chip select) pin must be deselected for a minimum of t csmin . the falling edge of cs w ill start the self clocking clear cycle of all memory locations in the device. the clocking of the sk pin is not necessary after the device has entered the self clocking mode. the ready/busy status of the cat130xx can be determi? ned by selecting the device and polling the do pin. once cleared, the contents of all memory bits return to a logical ?1? state. figure 7. erase instruction timing figure 8. eral instruction timing sk cs di do standby high-z high-z 1 a n a n-1 busy ready status verify t sv t hz t ew t cs 11 a 0 sk cs di do standby t cs high-z high-z 10 1 busy ready status verify t sv t hz t ew 00
cat130xx doc. no. 1121 rev. a 10 ? 2007 catalyst semiconductor, inc. characteristics subject to change without notice write all upon receiving a wral command and data, the cs (chip select) pin must be deselected for a minimum of t csmin (figure 9). the falling edge of cs will start the self clocking data write to all memory locations in the device. the clocking of the sk pin is not necessary after the device has entered the self clocking mode. the ready/busy status of the cat130xx can be deter? mined by selecting the device and polling the do pin. it is not necessary for all memory locations to be cleared before the wral command is executed. figure 9. wral instruction timing status verify sk cs di do standby high-z 10 1 busy ready t sv t hz t ew t csmin d n d 0 0 0
cat130xx ? 2007 catalyst semiconductor, inc. 11 doc. no. 1121 rev. a characteristics subject to change without notice package outlines 8-lead 150 mil soic (w) notes: (1) all dimensions are in millimeters. (2) complies with jedec specification ms-012 dimensions. symbol a1 a b c d e e1 h l min 0.10 1.35 0.33 4.80 5.80 3.80 0.25 0.40 nom 0.25 0.19 max 0.25 1.75 0.51 5.00 6.20 4.00 e 1.27 bsc 0.50 1.27 q1 0 8 e e1 d a1 e l q1 c b h x 45 a for current tape and reel information, download the pdf file from: http://www.catsemi.com/documents/tapeandreel.pdf.
cat130xx doc. no. 1121 rev. a 12 ? 2007 catalyst semiconductor, inc. characteristics subject to change without notice package marking 8-lead soic 130xxzwi 4yywwa csi = catalyst semiconductor, inc. xx = device code (see marking code table below) z = supervisory output code (see marking code table below) i = temperature range yy = production year ww = production week a = product revision 4 = lead finish nipdau device marking codes xx 13001 01 13004 04 13008 08 13016 16 supervisory marking codes z output active low 9 output active high 1
cat130xx ? 2007 catalyst semiconductor, inc. 13 doc. no. 1121 rev. a characteristics subject to change without notice example of ordering information notes: (1) all packages are rohs-comp liant (lead-free, halogen-free). (2) the standard lead finish is nipd au pre-plated (ppf) lead frames. (3) the device used in the above example is a CAT130019swi-gt3 (1kb eeprom, with active low cmos output, with a reset threshold between 2.85v - 3.00v, in an soic, industrial temperature, nipdau, tape and reel. (4) for additional package and temperature options, please contact your nearest ca talyst semiconductor sales office. (5) for 8-kb and 16-kb embedded eeprom option availability please contact your nearest catalyst semiconductor sales office. prefix device # suffix cat 13001 9 s w i - g t3 company id package w: soic reset threshold voltage l: 4.50v ? 4.75v m: 4.25v ? 4.50v j: 3.89v ? 4.10v t: 3.00v ? 3.15v s: 2.85v ? 3.00v r: 2.55v ? 2.70v z: 2.25v ? 2.38v lead finish g: nipdau (ppf) temperature range i = industrial (-40oc to 85oc) product type with memory density 13001: 1-kb eeprom 13004: 4-kb eeprom 13008 (5) : 8-kb eeprom 13016 (5) : 16-kb eeprom supervisor output type 9: cmos active low 1: cmos active high tape & reel t: tape & reel 3: 3000 units / reel
revision history date rev. reason 01/17/07 a initial issue copyrights, trademarks and patents trademarks and register ed trademarks of catalyst semiconductor include each of the following: beyond memory?, dpp?, ezdim?, minipot?, and quad-mode? catalyst semiconductor has been issued u. s. and foreign patents and has patent applicat ions pending that protect its products. catalyst semiconductor makes no warranty, representation or gu arantee, express or implied, regarding the suitability of its products for any particular purpose, nor that the use of its pro ducts will not infringe its intellectual property rights or the rights of third parties with respect to any particular use or application and specifically disclaims any and all liability aris ing out of any such use or application, including but not limited to, consequential or incidental damages. catalyst semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgica l implant into the body, or other applications intended to support or sustain life, or for any ot her application in which the failure of the catalyst semiconduct or product could create a situation where personal injury or death may occur. catalyst semiconductor reserves the right to make changes to or discontinue any product or se rvice described herein without not ice. products with data sheets labeled "advance information" or "preliminary" and other products described herein may not be in pr oduction or offered for sale. catalyst semiconductor advises customers to obtain the current version of the rele vant product informati on before placing order s. circuit diagrams illustrate typical semiconductor applications and may not be complete. catalyst semiconductor, inc. corporate headquarters 2975 stender way santa clara, ca 95054 phone: 408.542.1000 document no: 1121 fax: 408.542.1200 revision: a www.catsemi.com issue date: 01/17 / 07

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